Modelsim was installed only 3 weeks back and I don't think there is anything to do with licensing because I tried uninstalling modelsim, reinstalling and repeating the same process but again that was to no effect. I have enclosed a screenshot of my wave window. This procedure worked yesterday and is not working today. Here is a checklist of the procedure I followed.Ģ) I added counter.v and counter_tb.v to a project.ģ) I clicked "Start simulation" in the "Simulate menu"Ĥ) The I clicked my testbench module name under the work directory.ĥ) Then I clicked on the "Objects" tab and selected all the signals, right clicked, wave, add to wave all the signals in the design.Ħ) Now when I move to wave tab and click run icon i don't see any of the green waveforms. But today morning after I rebooted my laptop and tried opening modelsim and repeating the same process, I am not able to see any waveform on the wave window. Yesterday the simulation worked and I was able to see the waves in the modelsim wave window after adding the signals to the wave. I tried simulating a simple counter in modelsim pe student edition 10.0a. The configuration specification bound mux for DUT (a Mwidth_by_Ninputs_MUX virtual component).įixing the range constraints for the SEL and SLT to remain in bounds allows the simulation to run without an a bounds error.I have a perplexing problem and its very irritating.
You can constrain the declaration of SEL: sel : in integer range 0 to 2 ** n - 1 Īnd SLT to match: signal slt: integer range 0 to 2 ** 3 - 1 The declarations for SEL and SLT are at fault and the error is a run time error in mux for the assignment: y <= a(sel) Ī has a declared range of 0 to 2 ** N -1. The default initial value for SLT is INTEGER'LEFT (maximum negative integer value), out of bounds of a in mux. Your waveform format translates those to 'X's.įix those and something else will pop up. You non-specifically note the Y output isn't correct (outp is all 'U's, the default initial value). The missing component can't drive your outputs. Prompt 36 and you ran the simulation without the DUT. configuration specification added to map mux to Mwidth_by_Ninputs_MUXįor DUT: Mwidth_by_Ninputs_MUX use entity work.mux - ADDED The latter is done with a configuration specification: signal outp: std_logic_vector(8 - 1 downto 0) To cure it you can change name of mux or configure your testbench to use mux for Mwidth_by_by_Ninputs_MUX (DUT). Unbound component instance: it is essentially a null instance.
#Modelsim testbench code
Simulation can occur, but no VHDL code will be executed for the Ports and generics matching those of the component declaration, wasįound when searching all visible libraries for a default binding. To indicate the entity/architecture to use for that component.Īdditionally, no entity of the same name as the component, having Your VHDL design does not include a configuration specification orĬomponent configuration for the specified component instance in order Vsim Message # 3473: The specified component has not been explicitlyīound and no default binding has been found for it. Modelsim has verror that returns an expanded definition of what causes the error: Your instantiated component name doesn't match the name of the entity you compiled. Prompt 35 'restart' and you get a warning that component DUT is not bound. Signal outp : STD_LOGIC_VECTOR(8-1 downto 0) ĭUT: Mwidth_by_Ninputs_MUX port map(a => input, Signal slt : INTEGER -STD_LOGIC_VECTOR(3-1 downto 0)
Sel : IN INTEGER -STD_LOGIC_VECTOR(N-1 downto 0) PORT ( a : IN vector_array ((2**N)-1 downto 0) -,M-1 downto 0)
Y ) OF STD_LOGIC_VECTOR(8-1 downto 0) -(Natural RANGE ,Natural RANGE ) OF STD_LOGIC Īrchitecture Behavioral of tb_GenericMux is Signal test : STD_LOGIC_VECTOR(8-1 downto 0) PORT ( a : IN vector_array ((2**N)-1 downto 0) - ,M-1 downto 0) TYPE vector_array IS ARRAY (Natural RANGE ) OF STD_LOGIC_VECTOR(8-1 downto 0) -(Natural RANGE ,Natural RANGE ) OF STD_LOGIC I know this is a noob question, but I am a noob so that's ok. I've tried it several different ways with the OUTPUT y never making it out. I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created.
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